The present invention generally relates to off-loading tasks in an electronic system, and particularly relates to managing the flow of information between an application-specific component and other components using the memory access capabilities of a host processor.
Conventional electronic systems comprise various components, each component having a defined role within the system. For example, one or more host processors such as a General Purpose Processor (GPP) or a Central Processing Unit (CPU) controls overall system operation, e.g., by executing code and managing the flow of information within the system. Other components included in the system perform specific tasks, e.g., memory management, Input/Output (I/O) management, peripheral management, and limited or specialized data processing tasks.
Ever increasing performance demands create various bottlenecks within conventional systems. For example, memory and I/O interface bottlenecks hinder system performance. In addition, increased processing demands placed on a host processor further limit system efficiency since the host processor is tasked not only with executing performance-intensive code, but also with overseeing overall system operation such as I/O and memory management.
Special-purpose CPUs, e.g., a Digital Signal Processor may alleviate some processing demands placed on a host processor by handling certain types of tasks. Special-purpose CPUs are conventionally loosely coupled to a host processor in that they communicate with a host processor via a separate interface and have their own memory to which only they have direct access. Since a special-purpose CPU is loosely coupled to a host processor and has direct access to its own memory, it does not require direct control by the host processor to function. Instead, a special-purpose CPU is capable of independently accessing memory, fetching instructions, and executing code. Because special-purpose CPUs operate independently from a host processor, complex hardware and software is included in special-purpose CPUs for managing memory access.
A co-processor is yet another option for off-loading processing tasks assigned to a host processor, thereby allowing the host processor to utilize its processing resources for other tasks. Co-processors are designed for specific applications such as floating point arithmetic, graphics processing, broadband signal processing, encryption/decryption, etc. A co-processor is conventionally tightly coupled to a host processor in that the co-processor shares a single main memory with the host processor and operates under direction of the host processor. In addition, conventional co-processors execute instructions that are compliant with the instruction set architecture associated with the host processor. Unlike a special-purpose CPU, a co-processor is dependent upon a host processor for overseeing its operation since the co-processor does not have direct access to its own dedicated memory nor instruction fetch capability. Further, a co-processor is conventionally collocated with a host processor, and thus cannot be loosely coupled to the host processor, but instead operates under direct control of the host processor. As such, co-processors are conventionally dependant upon a host processor for fetching instructions, controlling co-processor instruction execution and handling all other operations aside from co-processor functions.